Mission critical systems are computer-based control systems that people depend on, often for their livelihoods, sometimes for their lives. As the integration scale of VLSI increases, computer-based systems are more prone to be affected by Single Event Upsets (SEUs). FPGAs have proven to be very useful devices for the injection of SEUs in order to assess the dependability of those systems. The conventional approach for injecting SEUs following the Run-Time Reconfiguration methodology involves reconfiguration times dependent on the complexity of the model. In case of complex models, it will greatly increase the execution time of fault injection experiments. This paper presents a new approach for the injection of SEUs into the memory elements of the system under test by means of FPGAs. This approach takes benefit of the FPGA architecture to minimise the reconfiguration time for SEU injection, obtaining an speed-up of near two orders of magnitude.